diff options
| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-05-09 16:34:13 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-05-09 16:34:13 +0000 |
| commit | 4d4c9e0757c95b259a39d3ba2d354c14ac30d47b (patch) | |
| tree | 188ecd0b060886ccda2482edcd2241ea06fd0f9b /llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp | |
| parent | 952391d8eb8a99f5fd731853bd3144daf81d85eb (diff) | |
| download | bcm5719-llvm-4d4c9e0757c95b259a39d3ba2d354c14ac30d47b.tar.gz bcm5719-llvm-4d4c9e0757c95b259a39d3ba2d354c14ac30d47b.zip | |
[AMDGPU] gfx1010 changes for PAL metadata
Differential Revision: https://reviews.llvm.org/D61704
llvm-svn: 360353
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp index 694f7c6dc75..0fd35231e7a 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp @@ -252,12 +252,15 @@ static const char *getRegisterName(unsigned RegNum) { {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"}, {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"}, {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"}, + {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"}, {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"}, {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"}, {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"}, {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"}, {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"}, {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"}, + {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"}, + {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"}, // Registers not known to code generation. {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"}, @@ -283,7 +286,6 @@ static const char *getRegisterName(unsigned RegNum) { {0xa1c5, "SPI_SHADER_COL_FORMAT"}, {0xa203, "DB_SHADER_CONTROL"}, {0xa08f, "CB_SHADER_MASK"}, - {0xa1b6, "SPI_PS_IN_CONTROL"}, {0xa191, "SPI_PS_INPUT_CNTL_0"}, {0xa192, "SPI_PS_INPUT_CNTL_1"}, {0xa193, "SPI_PS_INPUT_CNTL_2"}, @@ -334,7 +336,6 @@ static const char *getRegisterName(unsigned RegNum) { {0xa29b, "VGT_GS_OUT_PRIM_TYPE"}, {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"}, - {0xa2d5, "VGT_SHADER_STAGES_EN"}, {0xa2ad, "VGT_REUSE_OFF"}, {0xa1b8, "SPI_BARYC_CNTL"}, |
