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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-10-27 23:05:31 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-10-27 23:05:31 +0000 |
| commit | b133fbb9a49123f0caa05677d7d034ec7b0bdc09 (patch) | |
| tree | 05bdd490026c2291dc3fa70719c640c27e573871 /llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | |
| parent | 139a58f75ea887a6cc12623eb3e59187c3c5ce62 (diff) | |
| download | bcm5719-llvm-b133fbb9a49123f0caa05677d7d034ec7b0bdc09.tar.gz bcm5719-llvm-b133fbb9a49123f0caa05677d7d034ec7b0bdc09.zip | |
AMDGPU/SI: Handle hazard with > 8 byte VMEM stores
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25577
llvm-svn: 285359
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index 28e480b6f2a..484f681ab7d 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -158,6 +158,9 @@ bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo); bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo); /// \brief Get the size in bits of a register from the register class \p RC. +unsigned getRegBitWidth(unsigned RCID); + +/// \brief Get the size in bits of a register from the register class \p RC. unsigned getRegBitWidth(const MCRegisterClass &RC); /// \brief Get size of register operand |
