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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-27 18:49:11 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-27 18:49:11 +0000 |
| commit | 9be7b0d485088e001e13e84b12fbd86c3c92167e (patch) | |
| tree | 0871698ad21800ae5b5018f8630c576e67845ebd /llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | |
| parent | 10c7fb41874e8117f06e2dda0e234847526a695f (diff) | |
| download | bcm5719-llvm-9be7b0d485088e001e13e84b12fbd86c3c92167e.tar.gz bcm5719-llvm-9be7b0d485088e001e13e84b12fbd86c3c92167e.zip | |
AMDGPU: Add VOP3P instruction format
Add a few non-VOP3P but instructions related to packed.
Includes hack with dummy operands for the benefit of the assembler
llvm-svn: 296368
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index acc68afeaf2..c20a2093755 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -301,6 +301,8 @@ inline unsigned getOperandSize(const MCOperandInfo &OpInfo) { case AMDGPU::OPERAND_REG_IMM_FP16: case AMDGPU::OPERAND_REG_INLINE_C_INT16: case AMDGPU::OPERAND_REG_INLINE_C_FP16: + case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: + case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: return 2; default: @@ -323,6 +325,9 @@ bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi); LLVM_READNONE bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi); +LLVM_READNONE +bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi); + bool isUniformMMO(const MachineMemOperand *MMO); /// \returns The encoding that will be used for \p ByteOffset in the SMRD |
