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| author | Sam Tebbs <sam.tebbs@arm.com> | 2019-06-28 15:43:31 +0000 |
|---|---|---|
| committer | Sam Tebbs <sam.tebbs@arm.com> | 2019-06-28 15:43:31 +0000 |
| commit | e39e958da36da52d34e883dd5820262e96a8781a (patch) | |
| tree | 8531832a979744c37c7b8efe661600430bc5b2b9 /llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | |
| parent | 176b9f651685c52bce25e700a758bd33e6a5354d (diff) | |
| download | bcm5719-llvm-e39e958da36da52d34e883dd5820262e96a8781a.tar.gz bcm5719-llvm-e39e958da36da52d34e883dd5820262e96a8781a.zip | |
[ARM] Add support for the MVE long shift instructions
MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers.
The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl.
test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions.
Differential Revision: https://reviews.llvm.org/D63430
llvm-svn: 364654
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp')
0 files changed, 0 insertions, 0 deletions
