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| author | Florian Hahn <florian.hahn@arm.com> | 2017-05-23 09:33:34 +0000 |
|---|---|---|
| committer | Florian Hahn <florian.hahn@arm.com> | 2017-05-23 09:33:34 +0000 |
| commit | abb4218b988f6051cfc466a402b12dd91fb27c43 (patch) | |
| tree | 6096567314b53fd92a9124d6a1e28154955a210a /llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | |
| parent | 617be6e47596306a03b22f718dab00d986ac74a2 (diff) | |
| download | bcm5719-llvm-abb4218b988f6051cfc466a402b12dd91fb27c43.tar.gz bcm5719-llvm-abb4218b988f6051cfc466a402b12dd91fb27c43.zip | |
[AArch64] Make instruction fusion more aggressive.
Summary:
This patch makes instruction fusion more aggressive by
* adding artificial edges between the successors of FirstSU and
SecondSU, similar to BaseMemOpClusterMutation::clusterNeighboringMemOps.
* updating PostGenericScheduler::tryCandidate to keep clusters together,
similar to GenericScheduler::tryCandidate.
This change increases the number of AES instruction pairs generated on
Cortex-A57 and Cortex-A72. This doesn't change code at all in
most benchmarks or general code, but we've seen improvement on kernels
using AESE/AESMC and AESD/AESIMC.
Reviewers: evandro, kristof.beyls, t.p.northover, silviu.baranga, atrick, rengolin, MatzeB
Reviewed By: evandro
Subscribers: aemerson, rengolin, MatzeB, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33230
llvm-svn: 303618
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp')
0 files changed, 0 insertions, 0 deletions
