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author | Tom Stellard <thomas.stellard@amd.com> | 2017-01-27 18:41:14 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2017-01-27 18:41:14 +0000 |
commit | 08efb7ebf686a48a48b5d90a6ec264b58233829b (patch) | |
tree | 5bb98f09dad011f11dd1bf8b730ca6c27963b8c7 /llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | |
parent | fe12450e8e1b5b1daaab729700f1269c4b1f2095 (diff) | |
download | bcm5719-llvm-08efb7ebf686a48a48b5d90a6ec264b58233829b.tar.gz bcm5719-llvm-08efb7ebf686a48a48b5d90a6ec264b58233829b.zip |
AMDGPU/SI: Move some ISel helpers into utils so they can be shared with GISel
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D29068
llvm-svn: 293321
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 821f4e29ac7..e4eaaba9ec9 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -9,7 +9,9 @@ #include "AMDGPUBaseInfo.h" #include "AMDGPU.h" #include "SIDefines.h" +#include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/IR/LLVMContext.h" +#include "llvm/IR/Constants.h" #include "llvm/IR/Function.h" #include "llvm/IR/GlobalValue.h" #include "llvm/MC/MCContext.h" @@ -463,5 +465,32 @@ bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) { Val == 0x3118; // 1/2pi } +bool isUniformMMO(const MachineMemOperand *MMO) { + const Value *Ptr = MMO->getValue(); + // UndefValue means this is a load of a kernel input. These are uniform. + // Sometimes LDS instructions have constant pointers. + // If Ptr is null, then that means this mem operand contains a + // PseudoSourceValue like GOT. + if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) || + isa<Constant>(Ptr) || isa<GlobalValue>(Ptr)) + return true; + + const Instruction *I = dyn_cast<Instruction>(Ptr); + return I && I->getMetadata("amdgpu.uniform"); +} + +int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) { + if (isSI(ST) || isCI(ST)) + return ByteOffset >> 2; + + return ByteOffset; +} + +bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) { + int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset); + return isSI(ST) || isCI(ST) ? isUInt<8>(EncodedOffset) : + isUInt<20>(EncodedOffset); +} + } // End namespace AMDGPU } // End namespace llvm |