AMDGPU: Fix breaking VOP3 v_add_i32s

This was shrinking the instruction even though the carry output
register was a virtual register, not known VCC.

llvm-svn: 291716

1 files changed, 11 insertions, 1 deletions

diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index b27d7c69103..650eb33c111 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -84,7 +84,7 @@ static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
   // FIXME: v_cndmask_b32 has 3 operands and is shrinkable, but we need to add
   // a special case for it.  It can only be shrunk if the third operand
   // is vcc.  We should handle this the same way we handle vopc, by addding
-  // a register allocation hint pre-regalloc and then do the shrining
+  // a register allocation hint pre-regalloc and then do the shrinking
   // post-regalloc.
   if (Src2) {
     switch (MI.getOpcode()) {
@@ -456,6 +456,16 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
           continue;
       }
 
+      // Check for the bool flag output for instructions like V_ADD_I32_e64.
+      const MachineOperand *SDst = TII->getNamedOperand(MI,
+                                                        AMDGPU::OpName::sdst);
+      if (SDst && SDst->getReg() != AMDGPU::VCC) {
+        if (TargetRegisterInfo::isVirtualRegister(SDst->getReg()))
+          MRI.setRegAllocationHint(SDst->getReg(), 0, AMDGPU::VCC);
+
+        continue;
+      }
+
       // We can shrink this instruction
       DEBUG(dbgs() << "Shrinking " << MI);