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authorMatt Arsenault <Matthew.Arsenault@amd.com>2018-02-09 16:57:57 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2018-02-09 16:57:57 +0000
commit923712b6b516e1d3ce46f5bf1d9765f3dcfd5804 (patch)
tree173e47129bf6e0dae9a1b2693b914fff3146c590 /llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
parentbcf7bec4b861907ab0412cb6e92b31b884f15fbc (diff)
downloadbcm5719-llvm-923712b6b516e1d3ce46f5bf1d9765f3dcfd5804.tar.gz
bcm5719-llvm-923712b6b516e1d3ce46f5bf1d9765f3dcfd5804.zip
Reapply "AMDGPU: Add 32-bit constant address space"
This reverts r324494 and reapplies r324487. llvm-svn: 324747
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h')
-rw-r--r--llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 63875c55df0..6eed4fcd8ad 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -186,6 +186,8 @@ private:
// current hardware only allows a 16 bit value.
unsigned GITPtrHigh;
+ unsigned HighBitsOf32BitAddress;
+
MCPhysReg getNextUserSGPR() const {
assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
return AMDGPU::SGPR0 + NumUserSGPRs;
@@ -411,6 +413,10 @@ public:
return GITPtrHigh;
}
+ unsigned get32BitAddressHighBits() const {
+ return HighBitsOf32BitAddress;
+ }
+
unsigned getNumUserSGPRs() const {
return NumUserSGPRs;
}
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