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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-27 18:18:38 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-27 18:18:38 +0000 |
| commit | ff07631b481ee2396aa1bbaadefcbd537d787b08 (patch) | |
| tree | 7f5e75671677e3af966fb6af19711b9c0fb17931 /llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | |
| parent | fd10536a8c28a6acd8b642de2b38a8a1334bb383 (diff) | |
| download | bcm5719-llvm-ff07631b481ee2396aa1bbaadefcbd537d787b08.tar.gz bcm5719-llvm-ff07631b481ee2396aa1bbaadefcbd537d787b08.zip | |
AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization
llvm-svn: 370089
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index d9068d6d22f..58f4590daf9 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -486,6 +486,7 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo( NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()), MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()), + HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()), ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)), ScratchWaveOffsetReg(regToString(MFI.getScratchWaveOffsetReg(), TRI)), FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)), @@ -502,6 +503,7 @@ bool SIMachineFunctionInfo::initializeBaseYamlFields( ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize; MaxKernArgAlign = YamlMFI.MaxKernArgAlign; LDSSize = YamlMFI.LDSSize; + HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress; IsEntryFunction = YamlMFI.IsEntryFunction; NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath; MemoryBound = YamlMFI.MemoryBound; |
