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author | Konstantin Zhuravlyov <kzhuravl_dev@outlook.com> | 2016-06-25 03:11:28 +0000 |
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committer | Konstantin Zhuravlyov <kzhuravl_dev@outlook.com> | 2016-06-25 03:11:28 +0000 |
commit | f2f3d14774e6019048dccd1ecbca340ae5bbfca1 (patch) | |
tree | 65f692e2c2223031bede6426b5f4d1e6646d5655 /llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | |
parent | 92d33bd2af3452b7272f8d27a75c0e344ae20f38 (diff) | |
download | bcm5719-llvm-f2f3d14774e6019048dccd1ecbca340ae5bbfca1.tar.gz bcm5719-llvm-f2f3d14774e6019048dccd1ecbca340ae5bbfca1.zip |
[AMDGPU] Emit debugger prologue and emit the rest of the debugger fields in the kernel code header
Debugger prologue is emitted if -mattr=+amdgpu-debugger-emit-prologue.
Debugger prologue writes work group IDs and work item IDs to scratch memory at fixed location in the following format:
- offset 0: work group ID x
- offset 4: work group ID y
- offset 8: work group ID z
- offset 16: work item ID x
- offset 20: work item ID y
- offset 24: work item ID z
Set
- amd_kernel_code_t::debug_wavefront_private_segment_offset_sgpr to scratch wave offset reg
- amd_kernel_code_t::debug_private_segment_buffer_sgpr to scratch rsrc reg
- amd_kernel_code_t::is_debug_supported to true if all debugger features are enabled
Differential Revision: http://reviews.llvm.org/D20335
llvm-svn: 273769
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 6daebbaa0e4..0904d7dc8ab 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -54,6 +54,8 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) ReturnsVoid(true), MaximumWorkGroupSize(0), DebuggerReservedVGPRCount(0), + DebuggerWorkGroupIDStackObjectIndices{0, 0, 0}, + DebuggerWorkItemIDStackObjectIndices{0, 0, 0}, LDSWaveSpillSize(0), PSInputEna(0), NumUserSGPRs(0), @@ -92,16 +94,16 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) WorkItemIDX = true; } - if (F->hasFnAttribute("amdgpu-work-group-id-y")) + if (F->hasFnAttribute("amdgpu-work-group-id-y") || ST.debuggerEmitPrologue()) WorkGroupIDY = true; - if (F->hasFnAttribute("amdgpu-work-group-id-z")) + if (F->hasFnAttribute("amdgpu-work-group-id-z") || ST.debuggerEmitPrologue()) WorkGroupIDZ = true; - if (F->hasFnAttribute("amdgpu-work-item-id-y")) + if (F->hasFnAttribute("amdgpu-work-item-id-y") || ST.debuggerEmitPrologue()) WorkItemIDY = true; - if (F->hasFnAttribute("amdgpu-work-item-id-z")) + if (F->hasFnAttribute("amdgpu-work-item-id-z") || ST.debuggerEmitPrologue()) WorkItemIDZ = true; // X, XY, and XYZ are the only supported combinations, so make sure Y is |