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| author | NAKAMURA Takumi <geek4civic@gmail.com> | 2016-06-27 10:26:25 +0000 |
|---|---|---|
| committer | NAKAMURA Takumi <geek4civic@gmail.com> | 2016-06-27 10:26:25 +0000 |
| commit | d377ad806eec9aab01c02e6a2a26331b658286d7 (patch) | |
| tree | 59cfc8402d81c7cafa65321596a9b75c1dab134d /llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | |
| parent | 020a740b5b5b33aa3a55ab07bc817c8516d46b14 (diff) | |
| download | bcm5719-llvm-d377ad806eec9aab01c02e6a2a26331b658286d7.tar.gz bcm5719-llvm-d377ad806eec9aab01c02e6a2a26331b658286d7.zip | |
Reformat blank lines.
llvm-svn: 273858
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 0904d7dc8ab..529852b019e 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -7,7 +7,6 @@ // //===----------------------------------------------------------------------===// - #include "SIMachineFunctionInfo.h" #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" @@ -208,7 +207,6 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg ( // We have no VGPRs left for spilling SGPRs. return Spill; - LaneVGPRs[LaneVGPRIdx] = LaneVGPR; // Add this register as live-in to all blocks to avoid machine verifer |
