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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-24 18:05:16 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-24 18:05:16 +0000 |
| commit | 1c0ae3972f79c0d0bcbf15261308add2e6065358 (patch) | |
| tree | 3e4ade6dcabb82b03f677d82146a807e58588c33 /llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | |
| parent | b573b4b04d0471af4297a296206d7bdd0cd1955b (diff) | |
| download | bcm5719-llvm-1c0ae3972f79c0d0bcbf15261308add2e6065358.tar.gz bcm5719-llvm-1c0ae3972f79c0d0bcbf15261308add2e6065358.zip | |
AMDGPU: Add StackPtr and FramePtr registers to MFI
These will be necessary for setting up call sequences.
llvm-svn: 301208
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 8e612d2ddfd..b6a982aee6b 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -25,6 +25,8 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) TIDReg(AMDGPU::NoRegister), ScratchRSrcReg(AMDGPU::NoRegister), ScratchWaveOffsetReg(AMDGPU::NoRegister), + FrameOffsetReg(AMDGPU::NoRegister), + StackPtrOffsetReg(AMDGPU::NoRegister), PrivateSegmentBufferUserSGPR(AMDGPU::NoRegister), DispatchPtrUserSGPR(AMDGPU::NoRegister), QueuePtrUserSGPR(AMDGPU::NoRegister), |
