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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-06-22 20:08:27 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-06-22 20:08:27 +0000 |
| commit | f7f7068109262dda7a17155c59df3948fb2be65b (patch) | |
| tree | 47351ce9ea59fb02c985eec5fad5883ded5bef47 /llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | |
| parent | b4abcc55a3e116c3a91b6af9351f8e49a2419f43 (diff) | |
| download | bcm5719-llvm-f7f7068109262dda7a17155c59df3948fb2be65b.tar.gz bcm5719-llvm-f7f7068109262dda7a17155c59df3948fb2be65b.zip | |
[Hexagon] Add SDAG preprocessing step to expose shifted addressing modes
Transform: (store ch addr (add x (add (shl y c) e)))
to: (store ch addr (add x (shl (add y d) c))),
where e = (shl d c) for some integer d.
The purpose of this is to enable generation of loads/stores with
shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift
value c must be 0, 1 or 2.
llvm-svn: 273466
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp')
0 files changed, 0 insertions, 0 deletions
