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authorNicolai Haehnle <nhaehnle@gmail.com>2018-10-31 13:26:48 +0000
committerNicolai Haehnle <nhaehnle@gmail.com>2018-10-31 13:26:48 +0000
commit28212cc6891559855d41066d68e64a84097bb749 (patch)
tree58796a00d00b99291d0b62e166d4dce0242cb6a6 /llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
parent2efccd2cf2804e2143c67c01bdfa44c5e3d887ac (diff)
downloadbcm5719-llvm-28212cc6891559855d41066d68e64a84097bb749.tar.gz
bcm5719-llvm-28212cc6891559855d41066d68e64a84097bb749.zip
AMDGPU: Remove PHI loop condition optimization
Summary: The optimization to early break out of loops if all threads are dead was never fully implemented. But the PHI node analyzing is actually causing a number of problems, so remove all the extra code for it. (This does actually regress code quality in a few places because it ends up relying more heavily on phi's of i1, which we don't do a great job with. However, since it fixes real bugs in the wild, we should take this change. I have some prototype changes to improve i1 lowering in general -- not just for control flow -- which should help recover the code quality, I just need to make those changes fit for general consumption. -- Nicolai) Change-Id: I6fc6c6c8961857ac6009fcfb9f7e5e48dc23fbb1 Patch-by: Christian König <christian.koenig@amd.com> Reviewers: arsenm, rampitec, tpr Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D53359 llvm-svn: 345718
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp29
1 files changed, 0 insertions, 29 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index ad30317c344..1aa1feebbda 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -85,9 +85,7 @@ private:
void emitIf(MachineInstr &MI);
void emitElse(MachineInstr &MI);
- void emitBreak(MachineInstr &MI);
void emitIfBreak(MachineInstr &MI);
- void emitElseBreak(MachineInstr &MI);
void emitLoop(MachineInstr &MI);
void emitEndCf(MachineInstr &MI);
@@ -329,20 +327,6 @@ void SILowerControlFlow::emitElse(MachineInstr &MI) {
LIS->removeRegUnit(*MCRegUnitIterator(AMDGPU::EXEC, TRI));
}
-void SILowerControlFlow::emitBreak(MachineInstr &MI) {
- MachineBasicBlock &MBB = *MI.getParent();
- const DebugLoc &DL = MI.getDebugLoc();
- unsigned Dst = MI.getOperand(0).getReg();
-
- MachineInstr *Or = BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
- .addReg(AMDGPU::EXEC)
- .add(MI.getOperand(1));
-
- if (LIS)
- LIS->ReplaceMachineInstrInMaps(MI, *Or);
- MI.eraseFromParent();
-}
-
void SILowerControlFlow::emitIfBreak(MachineInstr &MI) {
MachineBasicBlock &MBB = *MI.getParent();
const DebugLoc &DL = MI.getDebugLoc();
@@ -384,11 +368,6 @@ void SILowerControlFlow::emitIfBreak(MachineInstr &MI) {
MI.eraseFromParent();
}
-void SILowerControlFlow::emitElseBreak(MachineInstr &MI) {
- // Lowered in the same way as emitIfBreak above.
- emitIfBreak(MI);
-}
-
void SILowerControlFlow::emitLoop(MachineInstr &MI) {
MachineBasicBlock &MBB = *MI.getParent();
const DebugLoc &DL = MI.getDebugLoc();
@@ -515,18 +494,10 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
emitElse(MI);
break;
- case AMDGPU::SI_BREAK:
- emitBreak(MI);
- break;
-
case AMDGPU::SI_IF_BREAK:
emitIfBreak(MI);
break;
- case AMDGPU::SI_ELSE_BREAK:
- emitElseBreak(MI);
- break;
-
case AMDGPU::SI_LOOP:
emitLoop(MI);
break;
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