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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-04-14 00:33:44 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-04-14 00:33:44 +0000 |
| commit | 86b0a5465be50b362c2a2748a5523a6f63778470 (patch) | |
| tree | b0efe4865c21a4909cf82fecdaa3cc5871125436 /llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | |
| parent | 8f56846d4f86efc9dccd5b64d569878191dcaaf5 (diff) | |
| download | bcm5719-llvm-86b0a5465be50b362c2a2748a5523a6f63778470.tar.gz bcm5719-llvm-86b0a5465be50b362c2a2748a5523a6f63778470.zip | |
[AMDGPU] added SIInstrInfo::getAddNoCarry() helper
Addressed rest of post submit comments from D31993.
Differential Revision: https://reviews.llvm.org/D32057
llvm-svn: 300288
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 41 |
1 files changed, 21 insertions, 20 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index 2689cad994b..933a1664674 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -385,17 +385,18 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair( BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); BaseRegFlags = RegState::Kill; BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::V_ADD_I32_e32), BaseReg) - .addImm(CI.BaseOff) - .addReg(AddrReg->getReg()); + .addImm(CI.BaseOff) + .addReg(AddrReg->getReg()); } - MachineInstrBuilder Read2 = BuildMI(*MBB, CI.Paired, DL, Read2Desc, DestReg) - .addReg(BaseReg, BaseRegFlags) // addr - .addImm(NewOffset0) // offset0 - .addImm(NewOffset1) // offset1 - .addImm(0) // gds - .addMemOperand(*CI.I->memoperands_begin()) - .addMemOperand(*CI.Paired->memoperands_begin()); + MachineInstrBuilder Read2 = + BuildMI(*MBB, CI.Paired, DL, Read2Desc, DestReg) + .addReg(BaseReg, BaseRegFlags) // addr + .addImm(NewOffset0) // offset0 + .addImm(NewOffset1) // offset1 + .addImm(0) // gds + .setMemRefs(CI.I->mergeMemRefsWith(*CI.Paired)); + (void)Read2; const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY); @@ -457,19 +458,19 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair( BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); BaseRegFlags = RegState::Kill; BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::V_ADD_I32_e32), BaseReg) - .addImm(CI.BaseOff) - .addReg(Addr->getReg()); + .addImm(CI.BaseOff) + .addReg(Addr->getReg()); } - MachineInstrBuilder Write2 = BuildMI(*MBB, CI.Paired, DL, Write2Desc) - .addReg(BaseReg, BaseRegFlags) // addr - .add(*Data0) // data0 - .add(*Data1) // data1 - .addImm(NewOffset0) // offset0 - .addImm(NewOffset1) // offset1 - .addImm(0) // gds - .addMemOperand(*CI.I->memoperands_begin()) - .addMemOperand(*CI.Paired->memoperands_begin()); + MachineInstrBuilder Write2 = + BuildMI(*MBB, CI.Paired, DL, Write2Desc) + .addReg(BaseReg, BaseRegFlags) // addr + .add(*Data0) // data0 + .add(*Data1) // data1 + .addImm(NewOffset0) // offset0 + .addImm(NewOffset1) // offset1 + .addImm(0) // gds + .setMemRefs(CI.I->mergeMemRefsWith(*CI.Paired)); moveInstsAfter(Write2, CI.InstsToMove); |
