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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-06-16 17:13:09 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-06-16 17:13:09 +0000 |
| commit | 52500216727e39fa90b33d914e93338c88b0abeb (patch) | |
| tree | f86e334dba0b0d62b25aef7b0329d0b934593af7 /llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | |
| parent | e20b388e2f923bfc98f63a13fea9fc19aeaec425 (diff) | |
| download | bcm5719-llvm-52500216727e39fa90b33d914e93338c88b0abeb.tar.gz bcm5719-llvm-52500216727e39fa90b33d914e93338c88b0abeb.zip | |
[AMDGPU] gfx10 conditional registers handling
This is cpp source part of wave32 support, excluding overriden
getRegClass().
Differential Revision: https://reviews.llvm.org/D63351
llvm-svn: 363513
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index 461f7b213d2..ae8b967893a 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -1144,9 +1144,10 @@ unsigned SILoadStoreOptimizer::computeBase(MachineInstr &MI, MachineOperand OffsetLo = createRegOrImm(static_cast<int32_t>(Addr.Offset), MI); MachineOperand OffsetHi = createRegOrImm(static_cast<int32_t>(Addr.Offset >> 32), MI); - unsigned CarryReg = MRI->createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); - unsigned DeadCarryReg = - MRI->createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); + + const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID); + unsigned CarryReg = MRI->createVirtualRegister(CarryRC); + unsigned DeadCarryReg = MRI->createVirtualRegister(CarryRC); unsigned DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); unsigned DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); |
