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authorDiana Picus <diana.picus@linaro.org>2017-01-13 09:58:52 +0000
committerDiana Picus <diana.picus@linaro.org>2017-01-13 09:58:52 +0000
commit116bbab4e4f440364bdaa900bc70d6c262a0b973 (patch)
treee3dc7375d120e028e5e16212b47cadf53753c87c /llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
parent4f8c3e18824278a2fc59f273af5793ee8d5e2618 (diff)
downloadbcm5719-llvm-116bbab4e4f440364bdaa900bc70d6c262a0b973.tar.gz
bcm5719-llvm-116bbab4e4f440364bdaa900bc70d6c262a0b973.zip
[CodeGen] Rename MachineInstrBuilder::addOperand. NFC
Rename from addOperand to just add, to match the other method that has been added to MachineInstrBuilder for adding more than just 1 operand. See https://reviews.llvm.org/D28057 for the whole discussion. Differential Revision: https://reviews.llvm.org/D28556 llvm-svn: 291891
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp42
1 files changed, 20 insertions, 22 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index 99fe96c0be2..ae5aefc2676 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -360,25 +360,24 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
unsigned DestReg = MRI->createVirtualRegister(SuperRC);
DebugLoc DL = I->getDebugLoc();
- MachineInstrBuilder Read2
- = BuildMI(*MBB, Paired, DL, Read2Desc, DestReg)
- .addOperand(*AddrReg) // addr
- .addImm(NewOffset0) // offset0
- .addImm(NewOffset1) // offset1
- .addImm(0) // gds
- .addMemOperand(*I->memoperands_begin())
- .addMemOperand(*Paired->memoperands_begin());
+ MachineInstrBuilder Read2 = BuildMI(*MBB, Paired, DL, Read2Desc, DestReg)
+ .add(*AddrReg) // addr
+ .addImm(NewOffset0) // offset0
+ .addImm(NewOffset1) // offset1
+ .addImm(0) // gds
+ .addMemOperand(*I->memoperands_begin())
+ .addMemOperand(*Paired->memoperands_begin());
(void)Read2;
const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
// Copy to the old destination registers.
BuildMI(*MBB, Paired, DL, CopyDesc)
- .addOperand(*Dest0) // Copy to same destination including flags and sub reg.
- .addReg(DestReg, 0, SubRegIdx0);
+ .add(*Dest0) // Copy to same destination including flags and sub reg.
+ .addReg(DestReg, 0, SubRegIdx0);
MachineInstr *Copy1 = BuildMI(*MBB, Paired, DL, CopyDesc)
- .addOperand(*Dest1)
- .addReg(DestReg, RegState::Kill, SubRegIdx1);
+ .add(*Dest1)
+ .addReg(DestReg, RegState::Kill, SubRegIdx1);
moveInstsAfter(Copy1, InstsToMove);
@@ -436,16 +435,15 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
const MCInstrDesc &Write2Desc = TII->get(Opc);
DebugLoc DL = I->getDebugLoc();
- MachineInstrBuilder Write2
- = BuildMI(*MBB, Paired, DL, Write2Desc)
- .addOperand(*Addr) // addr
- .addOperand(*Data0) // data0
- .addOperand(*Data1) // data1
- .addImm(NewOffset0) // offset0
- .addImm(NewOffset1) // offset1
- .addImm(0) // gds
- .addMemOperand(*I->memoperands_begin())
- .addMemOperand(*Paired->memoperands_begin());
+ MachineInstrBuilder Write2 = BuildMI(*MBB, Paired, DL, Write2Desc)
+ .add(*Addr) // addr
+ .add(*Data0) // data0
+ .add(*Data1) // data1
+ .addImm(NewOffset0) // offset0
+ .addImm(NewOffset1) // offset1
+ .addImm(0) // gds
+ .addMemOperand(*I->memoperands_begin())
+ .addMemOperand(*Paired->memoperands_begin());
moveInstsAfter(Write2, InstsToMove);
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