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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-09 22:44:48 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-09 22:44:48 +0000 |
| commit | 001826835a9b1381776e7c1c3b0ab7c8979fe555 (patch) | |
| tree | dd9622b069d1a20cbb7fe09dc9c68b6cfb38aac9 /llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | |
| parent | e114be608feb0878352ae2a41ded1bc4f3b9cb21 (diff) | |
| download | bcm5719-llvm-001826835a9b1381776e7c1c3b0ab7c8979fe555.tar.gz bcm5719-llvm-001826835a9b1381776e7c1c3b0ab7c8979fe555.zip | |
AMDGPU: Relax register classes used
llvm-svn: 374254
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index d0a6d03144d..a0821aa02d1 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -819,7 +819,7 @@ SILoadStoreOptimizer::mergeRead2Pair(CombineInfo &CI) { unsigned BaseSubReg = AddrReg->getSubReg(); unsigned BaseRegFlags = 0; if (CI.BaseOff) { - Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); + Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) .addImm(CI.BaseOff); @@ -912,7 +912,7 @@ SILoadStoreOptimizer::mergeWrite2Pair(CombineInfo &CI) { unsigned BaseSubReg = AddrReg->getSubReg(); unsigned BaseRegFlags = 0; if (CI.BaseOff) { - Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); + Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) .addImm(CI.BaseOff); |
