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| author | Duncan P. N. Exon Smith <dexonsmith@apple.com> | 2016-07-08 19:16:05 +0000 |
|---|---|---|
| committer | Duncan P. N. Exon Smith <dexonsmith@apple.com> | 2016-07-08 19:16:05 +0000 |
| commit | 4d295118944e911bb43cd8e8f92d6a70f746c7bd (patch) | |
| tree | 3b29a16f4c53ca83391c6f60efb9e63cd8268e4a /llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | |
| parent | d555bde59fd05819a2154255c798ead4d35e622a (diff) | |
| download | bcm5719-llvm-4d295118944e911bb43cd8e8f92d6a70f746c7bd.tar.gz bcm5719-llvm-4d295118944e911bb43cd8e8f92d6a70f746c7bd.zip | |
AMDGPU: Remove implicit iterator conversions, NFC
Remove remaining implicit conversions from MachineInstrBundleIterator to
MachineInstr* from the AMDGPU backend. In most cases, I made them less
attractive by preferring MachineInstr& or using a ranged-based for loop.
Once all the backends are fixed I'll make the operator explicit so that
this doesn't bitrot back.
llvm-svn: 274906
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index fc7aca22cef..4f1eb52c88a 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2946,15 +2946,15 @@ void SIInstrInfo::addSCCDefUsersToVALUWorklist( MachineInstr &SCCDefInst, SmallVectorImpl<MachineInstr *> &Worklist) const { // This assumes that all the users of SCC are in the same block // as the SCC def. - for (MachineBasicBlock::iterator I = SCCDefInst, - E = SCCDefInst.getParent()->end(); - I != E; ++I) { + for (MachineInstr &MI : + llvm::make_range(MachineBasicBlock::iterator(SCCDefInst), + SCCDefInst.getParent()->end())) { // Exit if we find another SCC def. - if (I->findRegisterDefOperandIdx(AMDGPU::SCC) != -1) + if (MI.findRegisterDefOperandIdx(AMDGPU::SCC) != -1) return; - if (I->findRegisterUseOperandIdx(AMDGPU::SCC) != -1) - Worklist.push_back(I); + if (MI.findRegisterUseOperandIdx(AMDGPU::SCC) != -1) + Worklist.push_back(&MI); } } |

