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authorHiroshi Inoue <inouehrs@jp.ibm.com>2018-02-22 07:48:29 +0000
committerHiroshi Inoue <inouehrs@jp.ibm.com>2018-02-22 07:48:29 +0000
commit7f9f92f8b68328a5d707a882674b846192f8f854 (patch)
tree46d8d9c202c605665db7cb48f48446058aaaf2b7 /llvm/lib/Target/AMDGPU/SIInsertWaits.cpp
parent663dbfadbf9c276a1124b5911dac46a0b68904fc (diff)
downloadbcm5719-llvm-7f9f92f8b68328a5d707a882674b846192f8f854.tar.gz
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[NFC] fix trivial typos in comments
"a a" -> "a" llvm-svn: 325752
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInsertWaits.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/SIInsertWaits.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp
index e89f0f855ed..d06d96be542 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp
@@ -218,7 +218,7 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) {
unsigned Size = TRI->getRegSizeInBits(*RC);
Result.Named.LGKM = Size > 32 ? 2 : 1;
} else {
- // s_dcache_inv etc. do not have a a destination register. Assume we
+ // s_dcache_inv etc. do not have a destination register. Assume we
// want a wait on these.
// XXX - What is the right value?
Result.Named.LGKM = 1;
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