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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-31 03:07:46 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-31 03:07:46 +0000 |
| commit | f84e5d9a2788d04b3f64e13fdb38c4172017a9c1 (patch) | |
| tree | bf4c117dcf7fdc1c9aa00bceaaf14e046594d29e /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | bc332648e8e3ce090c4ace3240809c349673d1a3 (diff) | |
| download | bcm5719-llvm-f84e5d9a2788d04b3f64e13fdb38c4172017a9c1.tar.gz bcm5719-llvm-f84e5d9a2788d04b3f64e13fdb38c4172017a9c1.zip | |
AMDGPU: Generalize matching of v_med3_f32
I think this is safe as long as no inputs are known to ever
be nans.
Also add an intrinsic for fmed3 to be able to handle all safe
math cases.
llvm-svn: 293598
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 89d3a72fae4..7e49fc28703 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -2795,6 +2795,9 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getNode(AMDGPUISD::SETCC, DL, VT, Op.getOperand(1), Op.getOperand(2), DAG.getCondCode(CCOpcode)); } + case Intrinsic::amdgcn_fmed3: + return DAG.getNode(AMDGPUISD::FMED3, DL, VT, + Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); case Intrinsic::amdgcn_fmul_legacy: return DAG.getNode(AMDGPUISD::FMUL_LEGACY, DL, VT, Op.getOperand(1), Op.getOperand(2)); |
