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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-10 02:42:31 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-10 02:42:31 +0000 |
| commit | b4493e909f269d5a9f6e6f356543ab80b2ad18d8 (patch) | |
| tree | c803d2f49411ade823d089e8254d48d90febe7ba /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | afe4aa8b2c69630c4cd5f40cc506bccef279ba17 (diff) | |
| download | bcm5719-llvm-b4493e909f269d5a9f6e6f356543ab80b2ad18d8.tar.gz bcm5719-llvm-b4493e909f269d5a9f6e6f356543ab80b2ad18d8.zip | |
AMDGPU: Fix trailing whitespace
llvm-svn: 294694
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index ba3a6232212..5c8aee79fdb 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1782,7 +1782,7 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter( switch (MI.getOpcode()) { case AMDGPU::S_TRAP_PSEUDO: { const DebugLoc &DL = MI.getDebugLoc(); - const int TrapType = MI.getOperand(0).getImm(); + const int TrapType = MI.getOperand(0).getImm(); if (Subtarget->getTrapHandlerAbi() == SISubtarget::TrapHandlerAbiHsa && Subtarget->isTrapHandlerEnabled()) { @@ -1798,11 +1798,11 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter( BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::SGPR0_SGPR1) .addReg(UserSGPR); BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_TRAP)) - .addImm(TrapType) + .addImm(TrapType) .addReg(AMDGPU::SGPR0_SGPR1, RegState::Implicit); } else { - switch (TrapType) { - case SISubtarget::TrapCodeLLVMTrap: + switch (TrapType) { + case SISubtarget::TrapCodeLLVMTrap: BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_ENDPGM)); break; case SISubtarget::TrapCodeLLVMDebugTrap: { @@ -1810,7 +1810,7 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter( "debugtrap handler not supported", DL, DS_Warning); - LLVMContext &C = MF->getFunction()->getContext(); + LLVMContext &C = MF->getFunction()->getContext(); C.diagnose(NoTrap); BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_NOP)) .addImm(0); @@ -1824,7 +1824,6 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter( MI.eraseFromParent(); return BB; } - case AMDGPU::SI_INIT_M0: BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) |
