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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-21 22:50:41 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-21 22:50:41 +0000 |
| commit | 7d6b71db4f7297940f0cf7787c0e2ad2ddb41252 (patch) | |
| tree | b8fae3a87ac222b34465bfd69f628f5ca13c0dc9 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | f0a4823b919a07a53bf8e5b4e5f5f4a75660f29e (diff) | |
| download | bcm5719-llvm-7d6b71db4f7297940f0cf7787c0e2ad2ddb41252.tar.gz bcm5719-llvm-7d6b71db4f7297940f0cf7787c0e2ad2ddb41252.zip | |
AMDGPU: Formatting fixes
llvm-svn: 295783
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index b0410b56cf3..60acf4fb1c0 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1533,11 +1533,12 @@ static bool setM0ToIndexFromSGPR(const SIInstrInfo *TII, } if (Offset == 0) { - BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0).add(*Idx); + BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) + .add(*Idx); } else { BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) - .add(*Idx) - .addImm(Offset); + .add(*Idx) + .addImm(Offset); } return true; @@ -2872,7 +2873,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); switch (IntrinsicID) { - case Intrinsic::amdgcn_exp: { + case Intrinsic::amdgcn_exp: { const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(2)); const ConstantSDNode *En = cast<ConstantSDNode>(Op.getOperand(3)); const ConstantSDNode *Done = cast<ConstantSDNode>(Op.getOperand(8)); |
