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authorFarhana Aleen <farhana.aleen@gmail.com>2018-03-07 16:55:27 +0000
committerFarhana Aleen <farhana.aleen@gmail.com>2018-03-07 16:55:27 +0000
commit347d12b4ceb270f1c06f18008f07fcb0148497fb (patch)
tree5ff6a409b04cf86fa7bee8d6727c5169877c8ecf /llvm/lib/Target/AMDGPU/SIISelLowering.cpp
parentf8438e8e591880d7857161a7cc83655c3fd076ef (diff)
downloadbcm5719-llvm-347d12b4ceb270f1c06f18008f07fcb0148497fb.tar.gz
bcm5719-llvm-347d12b4ceb270f1c06f18008f07fcb0148497fb.zip
Revert "[AMDGPU] Widened vector length for global/constant address space."
This reverts commit ce988cc100dc65e7c6c727aff31ceb99231cab03. llvm-svn: 326907
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/SIISelLowering.cpp10
1 files changed, 2 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 68a45cb8817..54aef36333d 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3454,10 +3454,6 @@ bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
return false;
}
-static bool isDwordAligned(unsigned Alignment) {
- return Alignment % 4 == 0;
-}
-
//===----------------------------------------------------------------------===//
// Custom DAG Lowering Operations
//===----------------------------------------------------------------------===//
@@ -5357,10 +5353,9 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
"Custom lowering for non-i32 vectors hasn't been implemented.");
- unsigned Alignment = Load->getAlignment();
unsigned AS = Load->getAddressSpace();
if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
- AS, Alignment)) {
+ AS, Load->getAlignment())) {
SDValue Ops[2];
std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(Load, DAG);
return DAG.getMergeValues(Ops, DL);
@@ -5388,8 +5383,7 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
AS == AMDGPUASI.CONSTANT_ADDRESS_32BIT ||
AS == AMDGPUASI.GLOBAL_ADDRESS) {
if (Subtarget->getScalarizeGlobalBehavior() && !Op->isDivergent() &&
- !Load->isVolatile() && isMemOpHasNoClobberedMemOperand(Load) &&
- isDwordAligned(Alignment))
+ !Load->isVolatile() && isMemOpHasNoClobberedMemOperand(Load))
return SDValue();
// Non-uniform loads will be selected to MUBUF instructions, so they
// have the same legalization requirements as global and private
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