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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-11 22:29:19 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-11 22:29:19 +0000 |
| commit | fe78ffba92c01a1138e12746d3fc74dfd17e01a8 (patch) | |
| tree | 343810f8413bdaea9036ab6c5fe5324e50bbae89 /llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | |
| parent | 978b1667d2d26732d85bf5c92bec3a3961ff45aa (diff) | |
| download | bcm5719-llvm-fe78ffba92c01a1138e12746d3fc74dfd17e01a8.tar.gz bcm5719-llvm-fe78ffba92c01a1138e12746d3fc74dfd17e01a8.zip | |
AMDGPU: Fix folding reg_sequence into copy to phys reg
This was producing an illegal reg_sequence defining
a physical register with virtual register inputs.
llvm-svn: 299997
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 43cb15f502c..34cd6f704a1 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -198,6 +198,10 @@ static bool foldVGPRCopyIntoRegSequence(MachineInstr &MI, if (!CopyUse.isCopy()) return false; + // It is illegal to have vreg inputs to a physreg defining reg_sequence. + if (TargetRegisterInfo::isPhysicalRegister(CopyUse.getOperand(0).getReg())) + return false; + const TargetRegisterClass *SrcRC, *DstRC; std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); |
