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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-07-09 18:11:15 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-07-09 18:11:15 +0000 |
| commit | 52a4d9b4297832a51a75cdb57d0015ffb1899a63 (patch) | |
| tree | 5cda6b36e248d7455fb1786d7231855f59c6814d /llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp | |
| parent | 48d70cb4862050446de3207ee22bba780c556a7e (diff) | |
| download | bcm5719-llvm-52a4d9b4297832a51a75cdb57d0015ffb1899a63.tar.gz bcm5719-llvm-52a4d9b4297832a51a75cdb57d0015ffb1899a63.zip | |
AMDGPU: Move R600 only pieces into R600 classes
llvm-svn: 274979
Diffstat (limited to 'llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp b/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp index 4c3a3f730fe..dfdc602b80c 100644 --- a/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp @@ -89,3 +89,10 @@ bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const { return true; } } + +void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, + int SPAdj, + unsigned FIOperandNum, + RegScavenger *RS) const { + llvm_unreachable("Subroutines not supported yet"); +} |
