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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2017-08-24 14:47:06 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2017-08-24 14:47:06 +0000 |
| commit | b0eb5fb317cbe831badc4da5843b1d526eff758a (patch) | |
| tree | 5bad3561b183330982f728d67b5cdd06d978c660 /llvm/lib/Target/AMDGPU/R600Packetizer.cpp | |
| parent | 5d67d8916e711daf4dd961d27f49ed408938be7c (diff) | |
| download | bcm5719-llvm-b0eb5fb317cbe831badc4da5843b1d526eff758a.tar.gz bcm5719-llvm-b0eb5fb317cbe831badc4da5843b1d526eff758a.zip | |
[AArch64] Add FMOVH0: materialize 0 using zero register for f16 values
Instead of loading 0 from a constant pool, it's of course much better to
materialize it using an fmov and the zero register.
Thanks to Ahmed Bougacha for the suggestion.
Differential Revision: https://reviews.llvm.org/D37102
llvm-svn: 311662
Diffstat (limited to 'llvm/lib/Target/AMDGPU/R600Packetizer.cpp')
0 files changed, 0 insertions, 0 deletions
