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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-26 04:49:24 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-26 04:49:24 +0000 |
| commit | bee7575e1ae9b4ec2a6fe1e02dc5bf9db33a4437 (patch) | |
| tree | ee9ffae066b69ef695721e3446529b3e36d14ebb /llvm/lib/Target/AMDGPU/R600Intrinsics.td | |
| parent | 382d945d162e76fc766bde894fd078d2592d39fa (diff) | |
| download | bcm5719-llvm-bee7575e1ae9b4ec2a6fe1e02dc5bf9db33a4437.tar.gz bcm5719-llvm-bee7575e1ae9b4ec2a6fe1e02dc5bf9db33a4437.zip | |
AMDGPU: Move AMDGPU intrinsics only used by R600
llvm-svn: 258790
Diffstat (limited to 'llvm/lib/Target/AMDGPU/R600Intrinsics.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/R600Intrinsics.td | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/R600Intrinsics.td b/llvm/lib/Target/AMDGPU/R600Intrinsics.td index 5fb8d412ae5..48e877f7d72 100644 --- a/llvm/lib/Target/AMDGPU/R600Intrinsics.td +++ b/llvm/lib/Target/AMDGPU/R600Intrinsics.td @@ -12,6 +12,18 @@ //===----------------------------------------------------------------------===// // FIXME: Should migrate to using TargetPrefix that matches triple arch name. +let TargetPrefix = "AMDGPU", isTarget = 1 in { + def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; + def int_AMDGPU_tex : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + def int_AMDGPU_txb : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + def int_AMDGPU_txf : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + def int_AMDGPU_txq : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + def int_AMDGPU_txd : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + def int_AMDGPU_txl : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + def int_AMDGPU_ddx : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + def int_AMDGPU_ddy : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; +} + let TargetPrefix = "R600", isTarget = 1 in { class TextureIntrinsicFloatInput : Intrinsic<[llvm_v4f32_ty], [ @@ -73,4 +85,4 @@ let TargetPrefix = "r600", isTarget = 1 in { def int_r600_txq : TextureIntrinsicInt32Input; def int_r600_ddx : TextureIntrinsicFloatInput; def int_r600_ddy : TextureIntrinsicFloatInput; -} +} // End TargetPrefix = "r600", isTarget = 1 |

