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author | Geoff Berry <gberry@codeaurora.org> | 2018-01-24 18:09:53 +0000 |
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committer | Geoff Berry <gberry@codeaurora.org> | 2018-01-24 18:09:53 +0000 |
commit | c4796d474572a03c97d0ddac4584b65c3e0e267f (patch) | |
tree | f23aaa1d3507a9beadc02a456199e02afa52811e /llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | |
parent | 4afb64e4c601e89f0645deb86de3784f5ff2927b (diff) | |
download | bcm5719-llvm-c4796d474572a03c97d0ddac4584b65c3e0e267f.tar.gz bcm5719-llvm-c4796d474572a03c97d0ddac4584b65c3e0e267f.zip |
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
Summary:
Move reserveRegisterTuples into AMDGPURegisterInfo and use it in
R600RegisterInfo::getReservedRegs and
R600InstrInfo::reserveIndirectRegisters to ensure that all super
registers of reserved registers are also marked as reserved.
Before this change, under certain circumstances, the registers %t1_x and
%t1_xyzw would be marked as reserved, but %t1_xy and %t1_xyz would not
be, leading to the register allocator sometimes assigning a register to
%t1_xy, which is invalid since %t1_x is reserved.
Reviewers: arsenm, tstellar, MatzeB, qcolombet
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D42448
llvm-svn: 323356
Diffstat (limited to 'llvm/lib/Target/AMDGPU/R600InstrInfo.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp index 23e646c8147..3e718f14c7f 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -1082,7 +1082,8 @@ bool R600InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { } void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved, - const MachineFunction &MF) const { + const MachineFunction &MF, + const R600RegisterInfo &TRI) const { const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>(); const R600FrameLowering *TFL = ST.getFrameLowering(); @@ -1093,11 +1094,9 @@ void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved, return; for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) { - unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index); - Reserved.set(SuperReg); for (unsigned Chan = 0; Chan < StackWidth; ++Chan) { unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan); - Reserved.set(Reg); + TRI.reserveRegisterTuples(Reserved, Reg); } } } |