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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-05-01 16:32:58 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-05-01 16:32:58 +0000 |
| commit | 692560dc986d90930887c0313249bc9fff798bf8 (patch) | |
| tree | 53610f5e08260b53aa5d8e6a14c0254d33209ae2 /llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | |
| parent | b3203ec078ca72919475093aca9fc19ca58dd272 (diff) | |
| download | bcm5719-llvm-692560dc986d90930887c0313249bc9fff798bf8.tar.gz bcm5719-llvm-692560dc986d90930887c0313249bc9fff798bf8.zip | |
[AMDGPU] gfx1010 MIMG implementation
Differential Revision: https://reviews.llvm.org/D61339
llvm-svn: 359698
Diffstat (limited to 'llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp index 205e9b3b584..04a30a5e26a 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -16,6 +16,7 @@ #include "MCTargetDesc/AMDGPUFixupKinds.h" #include "MCTargetDesc/AMDGPUMCCodeEmitter.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" +#include "SIDefines.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" @@ -273,7 +274,25 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff)); } - if (bytes > 4) + // NSA encoding. + if (AMDGPU::isGFX10(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { + int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(), + AMDGPU::OpName::vaddr0); + int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(), + AMDGPU::OpName::srsrc); + assert(vaddr0 >= 0 && srsrc > vaddr0); + unsigned NumExtraAddrs = srsrc - vaddr0 - 1; + unsigned NumPadding = (-NumExtraAddrs) & 3; + + for (unsigned i = 0; i < NumExtraAddrs; ++i) + OS.write((uint8_t)getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i), + Fixups, STI)); + for (unsigned i = 0; i < NumPadding; ++i) + OS.write(0); + } + + if ((bytes > 8 && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) || + (bytes > 4 && !STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal])) return; // Check for additional literals in SRC0/1/2 (Op 1/2/3) @@ -428,7 +447,8 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); if (AMDGPU::isSISrcOperand(Desc, OpNo)) { uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); - if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4)) + if (Enc != ~0U && + (Enc != 255 || Desc.getSize() == 4 || Desc.getSize() == 8)) return Enc; } else if (MO.isImm()) |
