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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-05-02 04:01:39 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-05-02 04:01:39 +0000 |
| commit | 5cf81677350812f455424b9bdbceb936183bb2c6 (patch) | |
| tree | 25c6c86916cbdeb43ed07b7a079fc389d63b5363 /llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | |
| parent | 9d744bcde993dffe05149be51a9c69178f7a6887 (diff) | |
| download | bcm5719-llvm-5cf81677350812f455424b9bdbceb936183bb2c6.tar.gz bcm5719-llvm-5cf81677350812f455424b9bdbceb936183bb2c6.zip | |
[AMDGPU] gfx1010 allows VOP3 to have a literal
Differential Revision: https://reviews.llvm.org/D61413
llvm-svn: 359756
Diffstat (limited to 'llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp index 04a30a5e26a..f2c666b31f6 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -249,6 +249,11 @@ uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO, // which does not have f16 support? return getLit16Encoding(static_cast<uint16_t>(Imm), STI); + case AMDGPU::OPERAND_REG_IMM_V2INT16: + case AMDGPU::OPERAND_REG_IMM_V2FP16: + if (!isUInt<16>(Imm) && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) + return getLit32Encoding(static_cast<uint32_t>(Imm), STI); + LLVM_FALLTHROUGH; case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: { uint16_t Lo16 = static_cast<uint16_t>(Imm); |
