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authorStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>2019-07-11 21:19:33 +0000
committerStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>2019-07-11 21:19:33 +0000
commite67cc380a800d91297bae9e82ea3357ff39e379d (patch)
treef5638751a2f622faef02c4a7533cc95fd82e8fef /llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
parent6bd26db06aae4fd27ea38f1aaac382005a079d29 (diff)
downloadbcm5719-llvm-e67cc380a800d91297bae9e82ea3357ff39e379d.tar.gz
bcm5719-llvm-e67cc380a800d91297bae9e82ea3357ff39e379d.zip
[AMDGPU] gfx908 mfma support
Differential Revision: https://reviews.llvm.org/D64584 llvm-svn: 365824
Diffstat (limited to 'llvm/lib/Target/AMDGPU/GCNRegPressure.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/GCNRegPressure.cpp8
1 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index be01988b6bc..39460fbd8a8 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -89,7 +89,9 @@ unsigned GCNRegPressure::getRegKind(unsigned Reg,
auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
return STI->isSGPRClass(RC) ?
(STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) :
- (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
+ STI->hasAGPRs(RC) ?
+ (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) :
+ (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
}
void GCNRegPressure::inc(unsigned Reg,
@@ -110,16 +112,18 @@ void GCNRegPressure::inc(unsigned Reg,
switch (auto Kind = getRegKind(Reg, MRI)) {
case SGPR32:
case VGPR32:
+ case AGPR32:
assert(PrevMask.none() && NewMask == MaxMask);
Value[Kind] += Sign;
break;
case SGPR_TUPLE:
case VGPR_TUPLE:
+ case AGPR_TUPLE:
assert(NewMask < MaxMask || NewMask == MaxMask);
assert(PrevMask < NewMask);
- Value[Kind == SGPR_TUPLE ? SGPR32 : VGPR32] +=
+ Value[Kind == SGPR_TUPLE ? SGPR32 : Kind == AGPR_TUPLE ? AGPR32 : VGPR32] +=
Sign * (~PrevMask & NewMask).getNumLanes();
if (PrevMask.none()) {
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