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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-26 13:39:29 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-26 13:39:29 +0000 |
| commit | e0b84434606117cf765c066d232626271591fe96 (patch) | |
| tree | 7cbef3b58417f52b9ab5ef89928dca2ca27b5184 /llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp | |
| parent | ed05d49aadc9441ad8afe13e6e164fbffe099929 (diff) | |
| download | bcm5719-llvm-e0b84434606117cf765c066d232626271591fe96.tar.gz bcm5719-llvm-e0b84434606117cf765c066d232626271591fe96.zip | |
AMDGPU: Check MRI for callee saved regs instead of TRI
This should the same, but MRI does allow dynamically changing the CSR
set, although currently not used.
llvm-svn: 364425
Diffstat (limited to 'llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp index fcbc3cddf6e..c3d076e95af 100644 --- a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp +++ b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp @@ -740,7 +740,7 @@ bool GCNRegBankReassign::runOnMachineFunction(MachineFunction &MF) { MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(Occupancy), MaxNumVGPRs); MaxNumSGPRs = std::min(ST->getMaxNumSGPRs(Occupancy, true), MaxNumSGPRs); - CSRegs = TRI->getCalleeSavedRegs(&MF); + CSRegs = MRI->getCalleeSavedRegs(); RegsUsed.resize(AMDGPU::VGPR_32RegClass.getNumRegs() + TRI->getEncodingValue(AMDGPU::SGPR_NULL) / 2 + 1); |
