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author | Eugene Zelenko <eugene.zelenko@gmail.com> | 2017-08-08 23:53:55 +0000 |
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committer | Eugene Zelenko <eugene.zelenko@gmail.com> | 2017-08-08 23:53:55 +0000 |
commit | d16eff816b876aac959dbd45dc78d41a06f966ad (patch) | |
tree | a306e9d295d76377cc82b0c802277d5d02e30a14 /llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp | |
parent | e5a9d9f17c1c577075e8a905618b2216d903b6f9 (diff) | |
download | bcm5719-llvm-d16eff816b876aac959dbd45dc78d41a06f966ad.tar.gz bcm5719-llvm-d16eff816b876aac959dbd45dc78d41a06f966ad.zip |
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 310429
Diffstat (limited to 'llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp | 32 |
1 files changed, 23 insertions, 9 deletions
diff --git a/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp index 0657f67b217..9904b5f0f4b 100644 --- a/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp +++ b/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp @@ -1,4 +1,4 @@ -//===----------------------- GCNMinRegStrategy.cpp - ----------------------===// +//===- GCNMinRegStrategy.cpp ----------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,18 +6,27 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// -/// \file -// -//===----------------------------------------------------------------------===// +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/ilist_node.h" +#include "llvm/ADT/simple_ilist.h" #include "llvm/CodeGen/ScheduleDAG.h" +#include "llvm/Support/Allocator.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" +#include <cassert> +#include <cstdint> +#include <limits> +#include <vector> using namespace llvm; #define DEBUG_TYPE "machine-scheduler" namespace { + class GCNMinRegScheduler { struct Candidate : ilist_node<Candidate> { const SUnit *SU; @@ -28,7 +37,7 @@ class GCNMinRegScheduler { }; SpecificBumpPtrAllocator<Candidate> Alloc; - typedef simple_ilist<Candidate> Queue; + using Queue = simple_ilist<Candidate>; Queue RQ; // Ready queue std::vector<unsigned> NumPreds; @@ -72,7 +81,8 @@ public: std::vector<const SUnit*> schedule(ArrayRef<const SUnit*> TopRoots, const ScheduleDAG &DAG); }; -} // namespace + +} // end anonymous namespace void GCNMinRegScheduler::initNumPreds(const decltype(ScheduleDAG::SUnits) &SUnits) { NumPreds.resize(SUnits.size()); @@ -104,7 +114,9 @@ int GCNMinRegScheduler::getNotReadySuccessors(const SUnit *SU) const { template <typename Calc> unsigned GCNMinRegScheduler::findMax(unsigned Num, Calc C) { assert(!RQ.empty() && Num <= RQ.size()); - typedef decltype(C(*RQ.begin())) T; + + using T = decltype(C(*RQ.begin())) ; + T Max = std::numeric_limits<T>::min(); unsigned NumMax = 0; for (auto I = RQ.begin(); Num; --Num) { @@ -260,9 +272,11 @@ GCNMinRegScheduler::schedule(ArrayRef<const SUnit*> TopRoots, } namespace llvm { + std::vector<const SUnit*> makeMinRegSchedule(ArrayRef<const SUnit*> TopRoots, const ScheduleDAG &DAG) { GCNMinRegScheduler S; return S.schedule(TopRoots, DAG); } -} + +} // end namespace llvm |