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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2017-09-06 13:50:13 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2017-09-06 13:50:13 +0000 |
| commit | 523827145b555a06673c4c3b9113d5ffe3599cee (patch) | |
| tree | a8767fc5859354e892b9bf32dd7e8cc2442a1c8f /llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp | |
| parent | 1509da083a69fac63785708b9ac00d05f33445a8 (diff) | |
| download | bcm5719-llvm-523827145b555a06673c4c3b9113d5ffe3599cee.tar.gz bcm5719-llvm-523827145b555a06673c4c3b9113d5ffe3599cee.zip | |
AMDGPU: Make worst-case assumption about the wait states in inline assembly
Summary:
Mesa still uses a hack where empty inline assembly is used as a kind of
optimization barrier. This exposed a problem where not enough wait states
were inserted, because the hazard recognizer implicitly assumed that each
inline assembly "instruction" has at least one wait state.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D37205
llvm-svn: 312635
Diffstat (limited to 'llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index 400c4aae9e0..76c3ed76dd0 100644 --- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -225,7 +225,8 @@ int GCNHazardRecognizer::getWaitStatesSince( return WaitStates; unsigned Opcode = MI->getOpcode(); - if (Opcode == AMDGPU::DBG_VALUE || Opcode == AMDGPU::IMPLICIT_DEF) + if (Opcode == AMDGPU::DBG_VALUE || Opcode == AMDGPU::IMPLICIT_DEF || + Opcode == AMDGPU::INLINEASM) continue; } ++WaitStates; |
