[AMDGPU][MC] Corrected GATHER4 opcodes

See bug 36252: https://bugs.llvm.org/show_bug.cgi?id=36252

Differential Revision: https://reviews.llvm.org/D43874

Reviewers: artem.tamazov, arsenm
llvm-svn: 327278

1 files changed, 8 insertions, 3 deletions

diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 578fe50146e..75356e9a9d3 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -273,6 +273,11 @@ DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
 // Consequently, decoded instructions always show address
 // as if it has 1 dword, which could be not really so.
 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
+
+  if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4) {
+    return MCDisassembler::Success;
+  }
+
   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
                                            AMDGPU::OpName::vdst);
 
@@ -289,7 +294,7 @@ DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
   assert(DMaskIdx != -1);
   assert(TFEIdx != -1);
 
-  bool isAtomic = (VDstIdx != -1);
+  bool IsAtomic = (VDstIdx != -1);
 
   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
   if (DMask == 0)
@@ -310,7 +315,7 @@ DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
 
   int NewOpcode = -1;
 
-  if (isAtomic) {
+  if (IsAtomic) {
     if (DMask == 0x1 || DMask == 0x3 || DMask == 0xF) {
       NewOpcode = AMDGPU::getMaskedMIMGAtomicOp(*MCII, MI.getOpcode(), DstSize);
     }
@@ -342,7 +347,7 @@ DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
   // in the instruction encoding.
   MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
 
-  if (isAtomic) {
+  if (IsAtomic) {
     // Atomic operations have an additional operand (a copy of data)
     MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
   }