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| author | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2018-03-12 17:29:24 +0000 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com> | 2018-03-12 17:29:24 +0000 |
| commit | d98c97b4f99ea481093996f65ec93b24e616f6a9 (patch) | |
| tree | e7ee106973d387f0000d0f3c119170fc0a01d75f /llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | |
| parent | bca036b6691973887517a33954d127cb69316508 (diff) | |
| download | bcm5719-llvm-d98c97b4f99ea481093996f65ec93b24e616f6a9.tar.gz bcm5719-llvm-d98c97b4f99ea481093996f65ec93b24e616f6a9.zip | |
[AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction
See bug 36558: https://bugs.llvm.org/show_bug.cgi?id=36558
Differential Revision: https://reviews.llvm.org/D43950
Reviewers: artem.tamazov, arsenm
llvm-svn: 327299
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 9e2957e9c1a..f26e9c72e0c 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -864,7 +864,7 @@ private: unsigned& RegNum, unsigned& RegWidth, unsigned *DwordRegIndex); void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands, - bool IsAtomic, bool IsAtomicReturn); + bool IsAtomic, bool IsAtomicReturn, bool IsLds = false); void cvtDSImpl(MCInst &Inst, const OperandVector &Operands, bool IsGdsHardcoded); @@ -1093,6 +1093,7 @@ public: void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); } void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); } void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, true); } + void cvtMubufLds(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false, true); } void cvtMtbuf(MCInst &Inst, const OperandVector &Operands); AMDGPUOperand::Ptr defaultGLC() const; @@ -4106,7 +4107,10 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultTFE() const { void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst, const OperandVector &Operands, - bool IsAtomic, bool IsAtomicReturn) { + bool IsAtomic, + bool IsAtomicReturn, + bool IsLds) { + bool IsLdsOpcode = IsLds; bool HasLdsModifier = false; OptionalImmIndexMap OptionalIdx; assert(IsAtomicReturn ? IsAtomic : true); @@ -4146,10 +4150,11 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst, // optional modifiers and llvm asm matcher regards this 'lds' // modifier as an optional one. As a result, an lds version // of opcode may be selected even if it has no 'lds' modifier. - if (!HasLdsModifier) { + if (IsLdsOpcode && !HasLdsModifier) { int NoLdsOpcode = AMDGPU::getMUBUFNoLdsInst(Inst.getOpcode()); if (NoLdsOpcode != -1) { // Got lds version - correct it. Inst.setOpcode(NoLdsOpcode); + IsLdsOpcode = false; } } @@ -4165,7 +4170,7 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst, } addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC); - if (!HasLdsModifier) { // tfe is not legal with lds opcodes + if (!IsLdsOpcode) { // tfe is not legal with lds opcodes addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE); } } |
