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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-08-30 22:18:40 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-08-30 22:18:40 +0000 |
| commit | c8f8cda0cd5e621678c1d4c52be596524dcdf1cd (patch) | |
| tree | 6669341d232cd0b5b7882e6e196283701c997b0b /llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | |
| parent | 24775a0a6ccfeae5e091b5e9990cb910913c2963 (diff) | |
| download | bcm5719-llvm-c8f8cda0cd5e621678c1d4c52be596524dcdf1cd.tar.gz bcm5719-llvm-c8f8cda0cd5e621678c1d4c52be596524dcdf1cd.zip | |
AMDGPU: Correct operand types for v_mad_mix*
These aren't really packed instructions, so the default
op_sel_hi should be 0 since this indicates a conversion.
The operand types are scalar values that behave similar
to an f16 scalar that may be converted to f32.
Doesn't change the default printing for op_sel_hi, just
the parsing.
llvm-svn: 312179
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index e1de580437e..417f425bfeb 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -1074,7 +1074,10 @@ public: OptionalImmIndexMap &OptionalIdx); void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands); void cvtVOP3(MCInst &Inst, const OperandVector &Operands); + void cvtVOP3PImpl(MCInst &Inst, const OperandVector &Operands, + bool IsPacked); void cvtVOP3P(MCInst &Inst, const OperandVector &Operands); + void cvtVOP3P_NotPacked(MCInst &Inst, const OperandVector &Operands); void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands); @@ -4254,7 +4257,9 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) { cvtVOP3(Inst, Operands, OptionalIdx); } -void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) { +void AMDGPUAsmParser::cvtVOP3PImpl(MCInst &Inst, + const OperandVector &Operands, + bool IsPacked) { OptionalImmIndexMap OptIdx; cvtVOP3(Inst, Operands, OptIdx); @@ -4267,11 +4272,15 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) { int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi); if (OpSelHiIdx != -1) { - addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi, -1); + // TODO: Should we change the printing to match? + int DefaultVal = IsPacked ? -1 : 0; + addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi, + DefaultVal); } int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo); if (NegLoIdx != -1) { + assert(IsPacked); addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo); addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi); } @@ -4325,6 +4334,15 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) { } } +void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) { + cvtVOP3PImpl(Inst, Operands, true); +} + +void AMDGPUAsmParser::cvtVOP3P_NotPacked(MCInst &Inst, + const OperandVector &Operands) { + cvtVOP3PImpl(Inst, Operands, false); +} + //===----------------------------------------------------------------------===// // dpp //===----------------------------------------------------------------------===// |
