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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-12-05 20:31:49 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-12-05 20:31:49 +0000 |
| commit | 8a63cb90443b0fde2a8dcf5a904ac3ebb3540e24 (patch) | |
| tree | a1ce812438e540dd38b49e349f1ee743313326d9 /llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | |
| parent | 0dd2306538e48c69bb41d2e3f81f25acedb18af6 (diff) | |
| download | bcm5719-llvm-8a63cb90443b0fde2a8dcf5a904ac3ebb3540e24.tar.gz bcm5719-llvm-8a63cb90443b0fde2a8dcf5a904ac3ebb3540e24.zip | |
AMDGPU: Change how exp is printed
This is an improvement over a long list of unreadable numbers.
A follow up patch will try to match how sc formats these.
llvm-svn: 288697
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 4ed2673dd77..81138a113c7 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -135,6 +135,8 @@ public: ImmTyDA, ImmTyR128, ImmTyLWE, + ImmTyExpCompr, + ImmTyExpVM, ImmTyHwreg, ImmTySendMsg, }; @@ -228,6 +230,8 @@ public: bool isDA() const { return isImmTy(ImmTyDA); } bool isR128() const { return isImmTy(ImmTyUNorm); } bool isLWE() const { return isImmTy(ImmTyLWE); } + bool isExpVM() const { return isImmTy(ImmTyExpVM); } + bool isExpCompr() const { return isImmTy(ImmTyExpCompr); } bool isOffen() const { return isImmTy(ImmTyOffen); } bool isIdxen() const { return isImmTy(ImmTyIdxen); } bool isAddr64() const { return isImmTy(ImmTyAddr64); } @@ -484,6 +488,8 @@ public: case ImmTyDA: OS << "DA"; break; case ImmTyR128: OS << "R128"; break; case ImmTyLWE: OS << "LWE"; break; + case ImmTyExpCompr: OS << "ExpCompr"; break; + case ImmTyExpVM: OS << "ExpVM"; break; case ImmTyHwreg: OS << "Hwreg"; break; case ImmTySendMsg: OS << "SendMsg"; break; } @@ -745,6 +751,8 @@ public: AMDGPUOperand::Ptr defaultSMRDOffset8() const; AMDGPUOperand::Ptr defaultSMRDOffset20() const; AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const; + AMDGPUOperand::Ptr defaultExpCompr() const; + AMDGPUOperand::Ptr defaultExpVM() const; OperandMatchResultTy parseOModOperand(OperandVector &Operands); @@ -2531,6 +2539,14 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultLWE() const { return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyLWE); } +AMDGPUOperand::Ptr AMDGPUAsmParser::defaultExpCompr() const { + return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyExpCompr); +} + +AMDGPUOperand::Ptr AMDGPUAsmParser::defaultExpVM() const { + return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyExpVM); +} + //===----------------------------------------------------------------------===// // smrd //===----------------------------------------------------------------------===// |

