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authorTom Stellard <thomas.stellard@amd.com>2012-07-16 14:17:08 +0000
committerTom Stellard <thomas.stellard@amd.com>2012-07-16 14:17:08 +0000
commitbcce80fa95e82ba9f7736525b81dbac577b5557e (patch)
tree34524b42c035f7838edc442c3b6da5a4ea88ca45 /llvm/lib/Target/AMDGPU/AMDILOperands.td
parent4273bb05d17ffdb18164b89a52f9fb1196acb51f (diff)
downloadbcm5719-llvm-bcce80fa95e82ba9f7736525b81dbac577b5557e.tar.gz
bcm5719-llvm-bcce80fa95e82ba9f7736525b81dbac577b5557e.zip
AMDGPU: Add core backend files for R600/SI codegen v6
llvm-svn: 160270
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDILOperands.td')
-rw-r--r--llvm/lib/Target/AMDGPU/AMDILOperands.td32
1 files changed, 32 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDILOperands.td b/llvm/lib/Target/AMDGPU/AMDILOperands.td
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+//===- AMDILOperands.td - AMD IL Operands ------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//==-----------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
+// Custom memory operand
+//===----------------------------------------------------------------------===//
+
+def MEMI32 : Operand<i32> {
+ let PrintMethod = "printMemOperand";
+ let MIOperandInfo = (ops GPRI32, GPRI32);
+}
+
+// Call target types
+def calltarget : Operand<i32>;
+def brtarget : Operand<OtherVT>;
+
+// def v2i8imm : Operand<v2i8>;
+// def v4i8imm : Operand<v4i8>;
+// def v2i16imm : Operand<v2i16>;
+// def v4i16imm : Operand<v4i16>;
+// def v2i32imm : Operand<v2i32>;
+// def v4i32imm : Operand<v4i32>;
+// def v2i64imm : Operand<v2i64>;
+// def v2f32imm : Operand<v2f32>;
+// def v4f32imm : Operand<v4f32>;
+// def v2f64imm : Operand<v2f64>;
+
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