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| author | Fangrui Song <maskray@google.com> | 2019-07-01 17:12:26 +0000 |
|---|---|---|
| committer | Fangrui Song <maskray@google.com> | 2019-07-01 17:12:26 +0000 |
| commit | ddc57afab9ef4e1cf708dc5454c0842c3e68f1e0 (patch) | |
| tree | 8ea6b9de3693c0c9dfb9a612e524945d412af5b5 /llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | |
| parent | f01fa40a00614fb2ca0282644375849e0aa650ce (diff) | |
| download | bcm5719-llvm-ddc57afab9ef4e1cf708dc5454c0842c3e68f1e0.tar.gz bcm5719-llvm-ddc57afab9ef4e1cf708dc5454c0842c3e68f1e0.zip | |
[ELF][RISCV] Support GD/LD/IE/LE TLS models
RISC-V psABI doesn't specify TLS relaxation. It can be handled the same
way as we handle ARM TLS. RISC-V TLS is even simpler because GD/LD use
the same relocation type.
Reviewed By: jrtc27, ruiu
Differential Revision: https://reviews.llvm.org/D63220
llvm-svn: 364813
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp')
0 files changed, 0 insertions, 0 deletions
