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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-05-31 16:57:45 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-05-31 16:57:45 +0000 |
| commit | ec30eb507e5bf3c5c5733f6a3beeacfc534fbb60 (patch) | |
| tree | 7a1a0e2db65736590f6ca5f501e3407b9e9acbb8 /llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | |
| parent | e18fc2130d20e33016d3ef49f6bf856cbe10e47f (diff) | |
| download | bcm5719-llvm-ec30eb507e5bf3c5c5733f6a3beeacfc534fbb60.tar.gz bcm5719-llvm-ec30eb507e5bf3c5c5733f6a3beeacfc534fbb60.zip | |
AMDGPU: Remove unused address space
Also return a single StringRef instead of building a string.
llvm-svn: 271296
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 087d90766be..b4d84a192a3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -77,18 +77,18 @@ static MachineSchedRegistry SISchedRegistry("si", "Run SI's custom scheduler", createSIMachineScheduler); -static std::string computeDataLayout(const Triple &TT) { - std::string Ret = "e-p:32:32"; - - if (TT.getArch() == Triple::amdgcn) { - // 32-bit private, local, and region pointers. 64-bit global and constant. - Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"; +static StringRef computeDataLayout(const Triple &TT) { + if (TT.getArch() == Triple::r600) { + // 32-bit pointers. + return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" + "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; } - Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256" - "-v512:512-v1024:1024-v2048:2048-n32:64"; - - return Ret; + // 32-bit private, local, and region pointers. 64-bit global, constant and + // flat. + return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" + "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" + "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; } LLVM_READNONE |
