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authorTom Stellard <thomas.stellard@amd.com>2016-03-03 03:53:29 +0000
committerTom Stellard <thomas.stellard@amd.com>2016-03-03 03:53:29 +0000
commitcc7067a668957bdbfba7e1d993b91e5737616fa8 (patch)
tree55b30099b8738d1748eaa4179950fbb799237002 /llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
parent2bbf7217eab497204acb7e6671b737d485c25547 (diff)
downloadbcm5719-llvm-cc7067a668957bdbfba7e1d993b91e5737616fa8.tar.gz
bcm5719-llvm-cc7067a668957bdbfba7e1d993b91e5737616fa8.zip
AMDGPU: Insert two S_NOP instructions for every high level source statement.
Patch by: Konstantin Zhuravlyov Summary: Tools, such as debugger, need to pause execution based on user input (i.e. breakpoint). In order to do this, two S_NOP instructions are inserted for each high level source statement: one before first isa instruction of high level source statement, and one after last isa instruction of high level source statement. Further, debugger may replace S_NOP instructions with S_TRAP instructions based on user input. Reviewers: tstellarAMD, arsenm Subscribers: echristo, dblaikie, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D17454 llvm-svn: 262579
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp11
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 32e9d8a9d19..df70b749d07 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -30,6 +30,7 @@
#include "llvm/IR/Verifier.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/IR/LegacyPassManager.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_os_ostream.h"
#include "llvm/Transforms/IPO.h"
@@ -54,6 +55,7 @@ extern "C" void LLVMInitializeAMDGPUTarget() {
initializeAMDGPUAnnotateUniformValuesPass(*PR);
initializeAMDGPUPromoteAllocaPass(*PR);
initializeSIAnnotateControlFlowPass(*PR);
+ initializeSIInsertNopsPass(*PR);
initializeSIInsertWaitsPass(*PR);
initializeSILowerControlFlowPass(*PR);
}
@@ -145,6 +147,12 @@ GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
//===----------------------------------------------------------------------===//
namespace {
+
+cl::opt<bool> InsertNops(
+ "amdgpu-insert-nops",
+ cl::desc("Insert two nop instructions for each high level source statement"),
+ cl::init(false));
+
class AMDGPUPassConfig : public TargetPassConfig {
public:
AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
@@ -364,6 +372,9 @@ void GCNPassConfig::addPreSched2() {
void GCNPassConfig::addPreEmitPass() {
addPass(createSIInsertWaitsPass(), false);
addPass(createSILowerControlFlowPass(), false);
+ if (InsertNops) {
+ addPass(createSIInsertNopsPass(), false);
+ }
}
TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
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