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authorMatt Arsenault <Matthew.Arsenault@amd.com>2016-10-06 16:56:41 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2016-10-06 16:56:41 +0000
commitd20a2dd7ac69f23c02f8b72eff99ff9af2ce0a47 (patch)
tree5ab0a9de463ec379c01dfad005fca802eebb473b /llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h
parentcb7110be27b566389b1636b3ac43eb0ea8762050 (diff)
downloadbcm5719-llvm-d20a2dd7ac69f23c02f8b72eff99ff9af2ce0a47.tar.gz
bcm5719-llvm-d20a2dd7ac69f23c02f8b72eff99ff9af2ce0a47.zip
AMDGPU: Support using tablegened MC pseudo expansions
Make the necessary refactorings to make use of PseudoInstExpansion llvm-svn: 283467
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h')
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h
index 8cedda6a706..57d2d85daec 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.h
@@ -20,6 +20,7 @@ class MachineOperand;
class MCContext;
class MCExpr;
class MCInst;
+class MCOperand;
class AMDGPUMCInstLower {
MCContext &Ctx;
@@ -33,6 +34,8 @@ public:
AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &ST,
const AsmPrinter &AP);
+ bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
+
/// \brief Lower a MachineInstr to an MCInst
void lower(const MachineInstr *MI, MCInst &OutMI) const;
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