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authorKyle Butt <kyle+llvm@iteratee.net>2017-05-17 21:54:41 +0000
committerKyle Butt <kyle+llvm@iteratee.net>2017-05-17 21:54:41 +0000
commitf6c61ef64d1293a0531cbcd0afeb2a401edd501e (patch)
tree1441f525eb865508738f3b765fa9f47738b4e9f2 /llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
parentab12984634c6614b5cb17390e0190562d248ed77 (diff)
downloadbcm5719-llvm-f6c61ef64d1293a0531cbcd0afeb2a401edd501e.tar.gz
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CodeGen: Power: Add lowering for shifts of v1i128.
When legalizing vector operations on vNi128, they will be split to v1i128 because that is a legal type on ppc64, but then the compiler will crash in selection dag because it fails to select for these operations. This patch fixes shift operations. Logical shift right and left shift can be performed in the vector unit, but algebraic shift right requires being split. Differential Revision: https://reviews.llvm.org/D32774 llvm-svn: 303307
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp')
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