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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-09 14:34:43 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-09 16:29:44 -0500 |
| commit | 35ad66fae811c36823b2b91368f142c9d35b8414 (patch) | |
| tree | c78e7eb4081c6cc06ca9cb03bbcb0f057cb962b7 /llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | |
| parent | 0c195ef7c62db1234e3854f8798e1ef413808b18 (diff) | |
| download | bcm5719-llvm-35ad66fae811c36823b2b91368f142c9d35b8414.tar.gz bcm5719-llvm-35ad66fae811c36823b2b91368f142c9d35b8414.zip | |
AMDGPU/GlobalISel: Widen 16-bit shift amount sources
This should be legal, but will require future selection work. 16-bit
shift amounts were already removed from being legal, but this didn't
adjust the transformation rules.
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 0e021701c1d..0b24493150a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -928,7 +928,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, } else Shifts.legalFor({{S16, S32}, {S16, S16}}); - Shifts.clampScalar(1, S16, S32); + // TODO: Support 16-bit shift amounts + Shifts.clampScalar(1, S32, S32); Shifts.clampScalar(0, S16, S64); Shifts.widenScalarToNextPow2(0, 16); } else { |
