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author | Tom Stellard <tstellar@redhat.com> | 2018-07-11 20:59:01 +0000 |
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committer | Tom Stellard <tstellar@redhat.com> | 2018-07-11 20:59:01 +0000 |
commit | 5bfbae5cb180ef00cc5ce412fd0fb6566918028e (patch) | |
tree | 2e41d4ce3a33a5e2606e3854bf5abd8bf3b97944 /llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | |
parent | 8027bb33308464a75f5644968da2ef6699625607 (diff) | |
download | bcm5719-llvm-5bfbae5cb180ef00cc5ce412fd0fb6566918028e.tar.gz bcm5719-llvm-5bfbae5cb180ef00cc5ce412fd0fb6566918028e.zip |
AMDGPU: Refactor Subtarget classes
Summary:
This is a follow-up to r335942.
- Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget
- Rename AMDGPUCommonSubtarget to AMDGPUSubtarget
- Merge R600Subtarget::Generation and GCNSubtarget::Generation into
AMDGPUSubtarget::Generation.
Reviewers: arsenm, jvesely
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D49037
llvm-svn: 336851
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h')
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index 07117272c33..0ffbc2e4edf 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -22,26 +22,27 @@ namespace { #define GET_GLOBALISEL_PREDICATE_BITSET +#define AMDGPUSubtarget GCNSubtarget #include "AMDGPUGenGlobalISel.inc" #undef GET_GLOBALISEL_PREDICATE_BITSET +#undef AMDGPUSubtarget } namespace llvm { class AMDGPUInstrInfo; class AMDGPURegisterBankInfo; -class AMDGPUSubtarget; +class GCNSubtarget; class MachineInstr; class MachineOperand; class MachineRegisterInfo; class SIInstrInfo; class SIMachineFunctionInfo; class SIRegisterInfo; -class SISubtarget; class AMDGPUInstructionSelector : public InstructionSelector { public: - AMDGPUInstructionSelector(const SISubtarget &STI, + AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM); @@ -91,11 +92,13 @@ private: const SIRegisterInfo &TRI; const AMDGPURegisterBankInfo &RBI; const AMDGPUTargetMachine &TM; - const SISubtarget &STI; + const GCNSubtarget &STI; bool EnableLateStructurizeCFG; #define GET_GLOBALISEL_PREDICATES_DECL +#define AMDGPUSubtarget GCNSubtarget #include "AMDGPUGenGlobalISel.inc" #undef GET_GLOBALISEL_PREDICATES_DECL +#undef AMDGPUSubtarget #define GET_GLOBALISEL_TEMPORARIES_DECL #include "AMDGPUGenGlobalISel.inc" |