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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-12 15:55:58 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-12 15:55:58 +0000 |
| commit | fd02314113546b7a90b1a26f957be7f5a855c790 (patch) | |
| tree | 39eaed286d59b671e9a341b1dd6116f0b5896822 /llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | |
| parent | 14d61436c010f3abca3c0081713951473b0f6d47 (diff) | |
| download | bcm5719-llvm-fd02314113546b7a90b1a26f957be7f5a855c790.tar.gz bcm5719-llvm-fd02314113546b7a90b1a26f957be7f5a855c790.zip | |
AMDGPU: Start adding offset fields to flat instructions
llvm-svn: 305194
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index a7eac080f88..e54c887d609 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -126,8 +126,9 @@ bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const { MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(AMDGPU::FLAT_STORE_DWORD)) .add(I.getOperand(1)) .add(I.getOperand(0)) - .addImm(0) - .addImm(0); + .addImm(0) // offset + .addImm(0) // glc + .addImm(0); // slc // Now that we selected an opcode, we need to constrain the register @@ -392,8 +393,9 @@ bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I) const { MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode)) .add(I.getOperand(0)) .addReg(PtrReg) - .addImm(0) - .addImm(0); + .addImm(0) // offset + .addImm(0) // glc + .addImm(0); // slc bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI); I.eraseFromParent(); |
