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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-09 18:29:37 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-09 18:29:37 +0000 |
| commit | d6c1f5bb154a0b524b92d15b99a882d654f906ce (patch) | |
| tree | e3316d930e32929c864488e3cf39692843c1ec66 /llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | |
| parent | 79f0d3a6e58b80e38040c9ef639431a268422058 (diff) | |
| download | bcm5719-llvm-d6c1f5bb154a0b524b92d15b99a882d654f906ce.tar.gz bcm5719-llvm-d6c1f5bb154a0b524b92d15b99a882d654f906ce.zip | |
AMDGPU/GlobalISel: Select fmed3
llvm-svn: 371435
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index aea9ad8cd20..c14a647a67c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -1504,6 +1504,25 @@ AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const { } InstructionSelector::ComplexRendererFns +AMDGPUInstructionSelector::selectVOP3OpSelMods0(MachineOperand &Root) const { + // FIXME: Handle clamp and op_sel + return {{ + [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }, + [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src_mods + [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // clamp + }}; +} + +InstructionSelector::ComplexRendererFns +AMDGPUInstructionSelector::selectVOP3OpSelMods(MachineOperand &Root) const { + // FIXME: Handle op_sel + return {{ + [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }, + [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // src_mods + }}; +} + +InstructionSelector::ComplexRendererFns AMDGPUInstructionSelector::selectSmrdImm(MachineOperand &Root) const { MachineRegisterInfo &MRI = Root.getParent()->getParent()->getParent()->getRegInfo(); |
