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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-05 02:20:25 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-05 02:20:25 +0000 |
commit | d51a3746d0c06f7267667cf8fdf0cfd27cbf304d (patch) | |
tree | d00caf97db9b8a292c41bd063be2f05ff0fb66d1 /llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | |
parent | 6d3ea2d9b60baf8db2dfeb3230bd8364a27fae30 (diff) | |
download | bcm5719-llvm-d51a3746d0c06f7267667cf8fdf0cfd27cbf304d.tar.gz bcm5719-llvm-d51a3746d0c06f7267667cf8fdf0cfd27cbf304d.zip |
AMDGPU/GlobalISel: Fix assert on load from constant address
llvm-svn: 371006
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 2fe463c190b..b0f4c2f36c3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -1137,13 +1137,13 @@ void AMDGPUInstructionSelector::getAddrModeInfo(const MachineInstr &Load, GEPInfo GEPInfo(*PtrMI); - for (unsigned i = 1, e = 3; i < e; ++i) { + for (unsigned i = 1; i != 3; ++i) { const MachineOperand &GEPOp = PtrMI->getOperand(i); const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg()); assert(OpDef); - if (isConstant(*OpDef)) { - // FIXME: Is it possible to have multiple Imm parts? Maybe if we - // are lacking other optimizations. + if (i == 2 && isConstant(*OpDef)) { + // TODO: Could handle constant base + variable offset, but a combine + // probably should have commuted it. assert(GEPInfo.Imm == 0); GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue(); continue; |